1. Technical Field of the Invention
The present invention relates to a device and method for recovering data accessed from random access memory cells, and particularly to a device and method for recovering bit line data from a dynamic random access memory (DRAM) cell.
2. Background of the Invention
Conventional DRAM cells employ a single transistor architecture wherein the memory cell comprises a storage capacitor having a first terminal connected to a reference voltage, such as Vss, and a second terminal connected to a pass and/or transmission gate transistor. The gate electrode of the pass/transmission gate transistor is tied to a word line decode signal and the drain electrode thereof is connected to a bit line. When a DRAM cell is read, the stored charge is shared between the capacitance of the storage capacitor and the capacitance of the corresponding bit line. The change in charge appearing on the bit lines following a memory cell read operation is small because the capacitance of the bit lines is significantly larger than the capacitance of the individual storage capacitors and because charge stored in a memory cell decays over time. Consequently, sense amplifiers are utilized to recover the full reference voltage level signal corresponding to the stored data.
The core of a DRAM is typically partitioned into arrays or blocks of memory cells, with each array including a plurality of rows of memory cells and with the cells in each row being connected to a respective one of a plurality of word lines. Memory cells in each column of cells in an array are connected to a respective one of a plurality of bit lines. Bit lines are grouped in pairs such that when data from a memory cell is read onto a first bit line of a bit line pair, the second bit line of the bit line pair is provided with a voltage level that is representative of a signal between a low logic level and a high logic level, relative to the amount of charge that can be placed thereon by a charged stored in a memory cell. This difference in voltage levels between the bit lines of the bit line pair is the differential to which an associated sense amplifier operatively responds.
The sense amplifier is connected to the bit lines to sense the small change in potential appearing on the bit lines following a memory cell read operation and to drive the bit lines to the appropriate full reference voltage level, such as Vdd or Vss. Once the sense amplifier drives the bit line to the full reference voltage level, the memory cell from which data was read is refreshed with the full reference voltage signal appearing on the bit line.
Sense amplifiers are operatively connected to a pair of bit lines from one or more memory arrays. Pass and/or transmission gates are employed between the sense amplifiers and the pairs of bit lines from adjacent memory arrays connected to the sense amplifier, in part to limit the capacitance appearing on the bit lines when the sense amplifiers are active, thereby decreasing the time necessary to perform a memory cell read and associated refresh operation. The pass/transmission gates additionally allow the bit lines of the selected bit line pair to incur a slight delay relative to the sense amplifier output nodes as the output nodes are being driven to full reference voltage levels, thereby increasing the speed at which the sense amplifier senses the charge differential of the bit line pair and drives its output nodes. However, because the pass gates usually comprise n-channel transistors, a sense amplifier is unable to drive its corresponding bit line to a full Vdd potential. Because a sense amplifier cannot store a full Vdd signal, representing a high logic level, into a memory cell and because a stored charge in a memory cell decays over time, a memory cell storing a high logic level is capable of maintaining the data only for a very limited period of time.
Attempts to overcome the aforementioned problem include employing CMOS pass gates in place of the n-channel pass gates. However, such implementations do not facilitate driving the bit lines by the sense amplifiers in a rapid manner. There remains a need for effectively driving DRAM bit lines and memory cells to full reference voltage levels quickly and accurately.